CVE Catalog

CVE-2025-54515

LowCVSS 1.0
Published: Updated: Translated: NVD NIST

Exploitation Probability (EPSS)

Low risk
0.12%

2th percentile - higher than 2% of all known CVEs

Summary

The Secure Flag passed to Versal Adaptive SoC's Trusted Firmware for Cortex-A processors (TF-A) for Arm's Power State Coordination Interface (PSCI) commands were incorrectly set to secure instead of using the processor's actual security state. This would allow the PSCI requests to appear they were from processors in the secure state instead of the non-secure state.

Risk Assessment

This could lead to misinterpretation of security state and potential bypass of isolation mechanisms between secure and non-secure worlds.

Recommendation

Apply the TF-A update provided by the vendor that corrects the Secure flag setting in PSCI commands.

Related vulnerabilities

Original NVD description (English source)

The Secure Flag passed to Versal™ Adaptive SoC’s Trusted Firmware for Cortex®-A processors (TF-A) for Arm’s Power State Coordination Interface (PSCI) commands were incorrectly set to secure instead of using the processor’s actual security state. This would allow the PSCI requests to appear they were from processors in the secure state instead of the non-secure state.

Vulnerability data from NVD (NIST) · CISA KEV · EPSS