CVE-2026-95109
HighCVSS 8.5Summary
The Cortex-A7 MMU Modules port validates a caller-supplied buffer by translating one address — the first byte. The common Module Manager hands its range check the module instance, the start address and the complete byte size; the Cortex-A7 implementation discarded the instance and the size and asked the MMU a single question about the start. A memory-protected module therefore passed any range whose first byte was user-readable, however far the rest of it reached. Privileged dispatch code then read or wrote the whole range.
Risk Assessment
Privileged dispatch code may read or write the entire memory range beyond allowed bounds, breaking module isolation and potentially exposing or modifying data. The flawed primitive is relied upon by all services using this macro.
Recommendation
Apply the vendor fix for the Cortex-A7 MMU Modules port that correctly validates the full range size. Until then, review modules using this primitive for exposure.
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Original NVD description (English source)
The Cortex-A7 MMU Modules port validates a caller-supplied buffer by translating **one address** — the first byte. The common Module Manager hands its range check the module instance, the start address and the complete byte size; the Cortex-A7 implementation discarded the instance and the size and asked the MMU a single question about the start. A memory-protected module therefore passed any range whose first byte was user-readable, however far the rest of it reached. Privileged dispatch code then read or wrote the whole range. Because every protected-module dispatcher that consumes a buffer or an extra-parameter array goes through this one macro, the defect is not in any individual service: it is in the primitive all of them rely on.
Vulnerability data from NVD (NIST) · CISA KEV · EPSS