CVE-2026-78119
MediumCVSS 6.3Exploitation Probability (EPSS)
Low risk1th percentile - higher than 1% of all known CVEs
Summary
The Nuvoton NPCX eSPI driver's espi_taf_parse() processes TAF requests without validating the 12-bit length field from the request header. For write and RPMC OP1 requests it copies up to 255 words into a fixed 16-word buffer in a static structure, causing an out-of-bounds write of roughly 956 bytes into .bss and reads past neighbouring eSPI registers. The same unvalidated length is passed to flash_write(), letting the host read up to 4 KB of adjacent controller SRAM.
Risk Assessment
The flaw is reachable only from the eSPI host side and only via a request that violates the negotiated payload size, so it requires host firmware or bus-level control. Consequences range from controller crash or hang to corruption of driver state that gates flash protection regions, crossing the trust boundary the TAF feature asserts.
Recommendation
Update to a version containing the fix that widens the counters, rejects requests exceeding ARRAY_SIZE(FLASHRXBUF) and NPCX_TAF_RX_PAYLOAD_WORDS, and marks such packets invalid. If CONFIG_ESPI_TAF is not required, disable it — no in-tree board enables it by default.
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Original NVD description (English source)
The Nuvoton NPCX eSPI driver parses Target-Attached-Flash (TAF) requests in espi_taf_parse() (drivers/espi/espi_npcx.c), taking the 12-bit length field directly out of the request header in the FLASHRXBUF FIFO. For write and RPMC OP1 requests it copied DIV_ROUND_UP(len, 4) words into struct espi_taf_pckt.src, a fixed 16-word (64-byte) member of a static structure, without ever comparing the length against that buffer or against the negotiated eSPI receive payload size (rx-plsize, 64 bytes on all in-tree NPCX/NPCK SoCs). Both the loop counter and the word count were uint8_t, so the copy ran up to 255 iterations. An eSPI controller that emits a flash request whose header claims a payload larger than the negotiated maximum therefore drives up to 239 32-bit stores past the end of the structure — roughly 956 bytes of out-of-bounds write into .bss — from the eSPI flash receive interrupt handler, while the source reads walk past the end of the 18-word FLASHRXBUF register array into neighbouring eSPI registers. The same unvalidated length was then passed on to flash_write() in espi_taf_npcx_flash_write() with the 64-byte src buffer as source, reading up to 4 KB of adjacent controller SRAM into SPI flash at a host-chosen address, where the host can read it back. A related fixed-size stack buffer in taf_npcx_completion_handler() was overflowed by four bytes on the maximum-size completion path on SoCs whose tx-plsize is 64. The defect is reachable only from the eSPI host side, and only by a request that violates the negotiated payload size, so it requires host firmware or bus-level control rather than ordinary host software; a compliant maximum-length write fits the buffer exactly and is handled correctly. Because TAF exists specifically so that the embedded controller arbitrates host access to shared flash (espi_taf_check_read_protect() / espi_taf_check_write_protect()), corrupting controller memory from a host-supplied field crosses the trust boundary the feature asserts; consequences range from controller crash or hang to corruption of driver state that gates the flash protection regions. The fix widens the counters, rejects any request whose word count exceeds both ARRAY_SIZE(FLASHRXBUF) - NPCX_ESPI_FLASH_HEADER_ADDRESS_LEN and NPCX_TAF_RX_PAYLOAD_WORDS (derived from the devicetree rx-plsize), marks such packets with a new invalid_flag so espi_taf_work() answers them with an unsuccessful completion instead of processing them, bounds the transmit payload against FLASHTXBUF, and adds a default case for unsupported cycle types. Only configurations with CONFIG_ESPI_TAF enabled on an NPCX/NPCK target are affected; no in-tree board enables it by default.
Vulnerability data from NVD (NIST) · CISA KEV · EPSS